By Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto
Analog Circuit layout comprises the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and necessary layout principles within the sector of analog circuit layout. every one half is gifted by way of six specialists in that box and cutting-edge details is shared and overviewed. This publication is quantity 20 during this winning sequence of Analog Circuit layout, delivering invaluable info and perfect overviews of:
Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief variety instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational assurance additionally makes it compatible to be used in a complicated layout path.
Read Online or Download Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC PDF
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Extra resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC
T. , Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009) Chapter 3 Low-Power Successive Approximation ADCS for Wireless Applications Jan Craninckx Abstract This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture.
M. , Honolulu, HI, USA, 2008, pp. 222–223 56. J. 44-mW pipelined ADC using dynamic source follower residue amplification. IEEE J. Solid-State Circuits 44(4), 1057–1066 (2009) 57. B. 2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS. IEEE J. Solid-State Circuits 45(10), 2080–2090 (2010) 58. T. 25–5 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS. IEEE J. Solid-State Circuits 44(11), 2901–2910 (2009) 59. R. , A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration.
2012 19 20 B. Murmann Flash Folding Two-Step Pipeline (Interleaved) Pipeline (1 Channel) SAR ΔΣ Other 100 fsrm s Jitter 1010 BW [Hz] 109 108 107 106 20 30 40 50 60 70 80 90 100 110 120 SNDR [dB] Fig. 1 Experimental data for ADC bandwidth (BW) versus SNDR. Pipelined ADCs dominate the 50–80 dB SNDR range for BW > 10 MHz the architectural landscape for conversion bandwidths above 10 MHz. Within this range, popular applications include wireless base stations , wireless LAN [7, 8], Ethernet transceivers , and medical ultrasound imagers .
Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC by Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto
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